1. Field of the Invention
The present invention relates to a semiconductor integrated circuit having memory cells. In particular, the present invention relates to a semiconductor integrated circuit having a redundancy circuit for relieving a defect in a memory cell or a defect in a peripheral circuit thereof.
2. Description of the Related Art
In general, semiconductor integrated circuits such as a DRAM have redundancy circuits so that lattice defects in their substrates and other defects resulting from particles produced in fabrication processes are relieved for an improved yield.
FIG. 1 shows the essential parts of a DRAM that has a redundancy circuit of this type. In the diagram, thick lines represent signal lines including a plurality of lines each.
The DRAM has an input circuit 2, a command decoder 4, an input buffer 6 for receiving a clock signal CLK, an address input circuit 8 for receiving an address signal ADD, a latching circuit 10, a predecoder 12, a column decoder 14, a fuse circuit 16, a redundancy judgement circuit 18, a redundancy predecoder 20, and a redundancy column decoder 22. The predecoder 12, column decoder 14, fuse circuit 16, redundancy judgement circuit 18, redundancy predecoder 20, and redundancy column decode 22 are circuits that operate in response to a supply of a column address. That is, this DRAM has a redundancy circuit for relieving a defect associated with a column address.
The input circuit 2 has an input buffer 2a for receiving command signals /CS, /RAS, /CAS, and /WE (hereinafter, these signals are collectively referred to as a command signal CMD), and a latch 2b for accepting the received signals in synchronization with an internal clock signal CLKINZ which is output from the input buffer 6. The command decoder 4 decodes the accepted command signal, and outputs command signals ACTV, READ, and WRITE, as well as an RAS address latching signal ERALPZ and a CAS address latching signal EXTPZ, depending on the decoding result.
The address input circuit 8 has an input buffer 8a for receiving the address signal ADD, and a latch 8b for accepting the received signal in synchronization with the internal clock signal CLKINZ. The latch 8b outputs the accepted signal as an internal address signal ADDIN. Incidentally, the DRAM of this example employs an address multiplex method, in which a row address or a column address is supplied to the DRAM as the address signal ADD.
The latching circuit 10 has a row latch 10a and a column latch 10b. The row latch 10a accepts a row address in synchronization with the RAS address latching signal ERALPZ, and outputs the accepted signal as a row address signal RADD. The row address signal RADD is supplied to not shown circuits associated with row addresses. The column latch 10b accepts a column address in synchronization with the CAS address latching signal EXTPZ, and outputs the accepted signal as a column address signal CADD.
The predecoder 12 accepts, when a redundancy judgement signal RDN is inactivated (at low level), the column address signal CADD in synchronization with a column enable pulse CEP which is generated by a not-shown control circuit. The predecoder 12 decodes the accepted signal to output a predetermined predecoding signal PDEC. The column decoder 14 decodes the predecoding signal PDEC, and activates a predetermined column line selecting signal CL.
The fuse circuit 16 includes a plurality of fuses formed of polysilicon or the like, and a control circuit thereof. The fuses are blown depending on a defect address (column address) found in a probe test under a wafer state. The fuse circuit 16 outputs the defect address set by the fuse blowing, as a redundancy column address signal RCADD. The redundancy judgement circuit 18 compares the column address signal CADD and the redundancy column address signal RCADD, and if these signals coincide with each other, activates (to high level) the redundancy judgement signal RDN.
The redundancy predecoder 20 accepts the redundancy judgement signal RDN in synchronization with the column enable pulse CEP, and outputs the accepted signal as a redundancy predecoding signal RPDEC. The redundancy column decoder 22 receives the redundancy predecoding signal RPDEC, and activates a redundancy column line selecting signal RCL The redundancy column line selecting signal RCL is activated when the comparison between the address signals CADD and RCADD in the redundancy judgement circuit 18 shows a coincidence. Then, the redundancy circuit operates to perform a read operation or a write operation on a not shown redundancy memory cell.
FIG. 2 shows an example of read operations by the DRAM shown in FIG. 1.
For a start, the command signal CMD (active command ACTV) and the address signal ADD (row address R1) are supplied to the DRAM in synchronization with the clock signal CLK. The latch 2b shown in FIG. 1 accepts the command signal CMD in synchronization with the internal clock signal CLKINZ (FIG. 2(a)). The latch 8b accepts the row address R1 in synchronization with the internal clock signal CLKINZ, and outputs the accepted address as the internal address signal ADDIN (FIG. 2(b)). Thereafter, a word line (not shown) corresponding to the row address R1 is selected.
In synchronization with the next clock signal CLK, the command signal CMD (read command READ) and the address signal ADD (column address C1) are supplied to the DRAM. Here, the column address C1 is an address corresponding to the location where a defect lies. Its information is written in the fuse circuit 16. The latch 8b accepts the column address C1 in synchronization with the internal clock signal CLKINZ, and outputs the accepted address as the internal address signal ADDIN (FIG. 2(c)).
The command decoder 4 receives the read command READ, and then turns the CAS address latching signal EXTPZ to high level after a predetermined period of time. The latch 10b accepts the column address C1 in synchronization with the rising edge of the CAS address latching signal EXTPZ, and outputs the accepted address as the column address signal CADD (FIG. 2(d)). The column address signal CADD is supplied to the predecoder 12 and the redundancy judgement circuit 18. The column address signal CADD (column address C1) coincides with the redundancy column address signal RCADD from the fuse circuit 16. Thus, the redundancy judgement circuit 18 turns the redundancy judgement signal RDN to high level (FIG. 2(e)). Here, the time T1 that elapses from the change of the column address signal CADD to the activation of the redundancy judgement signal RDN is the period necessary for the redundancy judgement circuit 18 to perform the redundancy judgement.
The activation of the redundancy judgement signal RDN inactivates the predecoder 12. The inactivation of the predecoder 12 disables operations on the normal memory cell corresponding to the column address C1. The redundancy predecoder 20 accepts the redundancy judgement signal RDN in synchronization with the rising edge of the column enable pulse CEP, and outputs the redundancy predecoding signal RPDEC (FIG. 2(f)). The redundancy column decoder 22 receives the redundancy predecoding signal RPDEC, and activates (to high level) the redundancy column line selecting signal RCL (FIG. 2(g)). The activation of the redundancy column line selecting signal RCL brings into conduction a column switch that is formed as the redundancy circuit. Thereby, data read from the redundancy memory cell (not shown) is output.
In synchronization with the next clock signal CLK, the command signal CMD (read command READ) and the address signal ADD (column address C2) are supplied to the DRAM. Here, the column address C2 is not an address corresponding to the defective portion. Therefore, the redundancy judgement circuit 18 turns the redundancy judgement signal RDN to low level (FIG. 2(h)).
The predecoder 12 is activated by the inactivation of the redundancy judgement signal RDN. The redundancy column decoder 22 is inactivated by the inactivation of the redundancy judgement signal RDN. The inactivation of the redundancy column decoder 22 disables operations on the redundancy memory cell. The predecoder 12 accepts the column address signal CADD in synchronization with the rising edge of the column enable pulse CEP, decodes the accepted signal, and outputs a predetermined predecoding signal PDEC (FIG. 2(i)).
The column decoder 14 decodes the predecoding signal PDEC, and activates (to high level) a predetermined column line selecting signal CL (FIG. 2(j)). The activation of the column line selecting signal CL brings a predetermined column switch into conduction, whereby data read from the memory cell (not shown) is output.
In the conventional DRAM described above, the inputting of an address, the latching, the redundancy judgement, and the decoding are executed in succession to their respective preceding processes. For example, the redundancy judgement circuit 18 receives the column address signal CADD generated through the address input circuit 8 and the latching circuit 10. In other words, the address comparison in the redundancy judgement circuit 18 is performed after the generation of the column address signal CADD. On this account, there has been a problem that the operating timing of the internal circuits lags as much as the time T1 mentioned above, thereby delaying the output of read data. That is, the access time cannot be reduced. This problem also occurs in write operations. More specifically, the write timing of write data into a memory cell lags as much as the time T1 which is necessary for a comparison between the write address and the defect address. The increased read operation time and write operation time prevent the clock signal being enhanced in frequency.
An object of the present invention is to reduce the amount of access times of a semiconductor integrated circuit which has memory cells and a redundancy circuit for relieving a defect.
Another object of the present invention is to perform redundancy judgement in the redundancy circuit at a earlier timing, thereby avoiding unnecessary operations of internal circuits, and reducing power consumption.
Still another object of the present invention is to make the operating timing of internal circuits equal regardless of addresses being normal or defective, thereby facilitating controlling the internal circuits.
Another object of the present invention is to provide a clock synchronous type semiconductor integrated circuit having memory cells, wherein read and write operations on a memory cell or a redundancy memory cell are controlled at higher speed, thereby heightening the frequency of a clock signal.
Another object of the present invention is to provide a semiconductor integrated circuit including memory cells to which row address signals and column address signals are sequentially supplied, wherein the redundancy judgement of the row address signal or the column address signal is performed at high speed.
According to one aspect of the present invention, a semiconductor integrated circuit includes memory cells, a redundancy memory cell for relieving a defect, an address input circuit, a latching circuit, a redundancy judgement circuit, and a redundancy latching circuit. The address input circuit receives an address signal supplied from the exterior, and outputs the received signal as an internal address signal. The latching circuit accepts the internal address signal from the address input circuit, and supplies the accepted signal to an internal circuit in conformity to the operating timing of the internal circuit. The redundancy judgement circuit receives the internal address signal from the address input circuit, judges whether or not the internal address signal received is of a defect address, and outputs the judgement result as a redundancy judgement signal. That is, the redundancy judgement signal is activated when the internal address signal is of a defect address. The redundancy latching circuit accepts the redundancy judgement signal, and supplies the accepted signal to the internal circuit in conformity to the operating timing of the internal circuit. Since the address signal before it is latched is thus used for the redundancy judgement, the redundancy judgement can be performed at a earlier timing. The redundancy judgement signal (the information of the redundancy address) can be latched after the redundancy judgement. This allows reduction in the amount of time needed for performing the read operation and the write operation to the memory cells or the redundancy memory cell. Moreover, since the redundancy judgement is performed at a early point in time during the operating cycle, access to normal memory cells can be disabled earlier in relieving a defect (when the redundancy judgement signal is activated). As a result, unnecessary operations of internal circuits associated with memory cell operations can be avoided thereby reducing power consumption.
According to another aspect of the present invention, the address input circuit outputs the received address signal initially as a first internal address signal, and then as a second internal address signal which is behind the first internal address signal in timing. For example, the time the second internal address signal is delayed compared to the first internal address signal is set to correspond to the time for the redundancy judgement circuit to make a defect address judgement. The redundancy judgement circuit receives the first internal address signal as the internal address signal. The latching circuit receives the second internal address signal as the internal address signal. This makes it possible to make the latching timing of the latching circuit equal to that of the redundancy latching circuit. Therefore, the operating timings of the internal circuit can be equalized irrespective of addresses being normal or defective. As a result, controlling the internal circuit is facilitated.
According to another aspect of the present invention, the address input circuit outputs the first internal address signal and the second internal address signal in synchronization with a clock signal supplied from exterior. Alternatively, the address input circuit outputs the first internal address signal not in synchronization, or in asynchronization, with a clock signal supplied from exterior, and outputs the second internal address signal in synchronization with the clock signal. Therefore, even in a semiconductor integrated circuit of clock synchronous type, read and write operations on a memory cell or a redundancy memory cell can be controlled at high speed. As a result, it becomes possible to heighten the frequency of the clock signal.
According to another aspect of the present invention, a read operation, a write operation, or the like is performed in accordance with an address signal that is successively supplied in twice. Here, the redundancy judgement circuit judges whether or not the address signal received first is of a defect address. Therefore, for example, in a semiconductor integrated circuit to which a row address signal and a column address signal are sequentially supplied, the redundancy judgement of the row address signal can be performed at high speed.
According to another aspect of the present invention, a read operation, a write operation, or the like is performed in accordance with an address signal that is successively supplied in twice. Here, the redundancy judgement circuit judges whether or not the address signal received second is of a defect address. Therefore, for example, in a semiconductor integrated circuit to which a row address signal and a column address signal are sequentially supplied, the redundancy judgement of the column address signal can be performed at high speed.